1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for improved integrated circuit layout techniques.
2. Description of the Related Art
In the design of integrated circuits, serious consideration is typically placed on ensuring that the circuit design not only meet operational specifications, but also anticipated fabrication imperfections. For example, when an integrated circuit is initially designed, all of the circuit elements and interconnections are characterized by numerous lines and shapes that are intended to lie on one or more levels of a device. It is therefore these lines and shapes of the integrated circuit device that will typically undergo the fabrication imperfections when the lines and shapes are fabricated onto a semiconductor wafer.
Typically, these imperfections are due to layers being deposited or grown at different rates throughout the surface of the wafer, to the etching variations, to diffusion dopant variations, to photolithography errors or misalignments, etc. Because these imperfections are anticipated by those who design integrated circuits on semiconductor devices, designers typically build some amount of tolerance into their designs. Commonly, these built-in tolerances are characterized by designing devices slightly larger than optimum, or designing devices having a less dense arrangement. Although most circuit devices can handle such imperfections by making a number of modifications to a design, balanced-type circuits are typically affected more severely, even when the fabrication imperfection is small.
Generally, a balanced circuit is one that requires complementary devices to have the same drive strength, to have the same input capacitance, and to have the same output load. For ease of description, FIG. 1A shows a cross-sectional view of a semiconductor device having a pair of transistors that may be part of a balanced circuit. In balanced circuits, the fabrication imperfections that occur between devices oriented in close proximity of each other is some times referred to as a "local mismatch." As used herein, a local mismatch may be between devices that are designed to be within about 20 microns of separation. These local mismatches are what cause an imbalance in the circuit that should ideally be balanced.
By way of example, the cross-sectional view of the semiconductor device shows a first transistor device 14 having diffusion regions 15, a gate oxide 18 and a polysilicon gate 16. Separated by a field oxide 13 is a second transistor device 20 that also has diffusion regions 15, a gate oxide 18' and the polysilicon gate 16. In this example, the diffusion regions 15 are n+ doped regions and a well 12 in a semiconductor wafer 10 is p+ doped. As illustrated, the gate oxide 18 in the first transistor device 14 has a thickness Ox (H), which is about 10% thinner than the gate oxide 18' in the second transistor device 20 that has a thickness of Ox (H+.DELTA.H). Because of this local mismatch, a balanced circuit that utilizes transistors 14 and 20 will necessarily experience unequal drive strength. For example, the first transistor device 14 will generally turn ON faster than the second transistor device 20 due to the thinner gate oxide thickness Ox (H).
Another problem that tends to occur during normal fabrication is an unequal application of impurities when the doping processes are performed. Again, FIG. 1A illustrates the doping profile in the well 12 that may occur when the region under the second transistor device 20 is doped with a high concentration of dopant atoms (i.e., p++), and the region under the first transistor 14 is doped with a lighter concentration of dopant atoms (i.e., p+). As pictorially shown, the doping profile has a depth of about D under the first transistor device 14, which increases up to about D+.DELTA.D under the second transistor device 20.
When this occurs, a channel 11 of the first transistor device 14 will form before a channel 11' forms in the second transistor device 20, because the mobility of the carriers in the diffusion region 15 is higher in channel 11. In addition, the lighter doping under the first transistor device 14 will provide improved current carrying capabilities over the second transistor device 20. As can be appreciated, these local mismatches will necessarily cause a balanced circuit, such as those used in memory sense amplifying circuitry to operate in a state that is less than optimum.
FIG. 1B shows another problem that may occur due to known and expected fabrication imperfections. FIG. 1B provides a top view 40 of a the semiconductor structure of FIG. 1A, which illustrates a problem. The problem is most evident in the etching imperfections that produced the widths of the polysilicon gates 16. For example, the length of the polysilicon gate 16 of the first transistor device 14 is shown to be L+.DELTA.L, while the length of the polysilicon gate 16 of the second transistor device 20 is only L. As is well known to those skilled in the art, when the length of a transistor is longer, the transistor will turn ON with less current drive than those with narrower gate lengths. As a result, the drive strength and input capacitance differences produced by the local mismatch of these transistors in, for example, balanced memory sense amplifying devices may be less than acceptable in a given application.
FIG. 1C is a top view of the semiconductor device of FIG. 1A, which is provided to illustrate yet another type of anticipated fabrication imperfection that is counterproductive in balanced circuit applications. In this example, the fabrication imperfection may be a result of misalignments in reticle masks used in a stepper apparatus that is used in the photolithography process. Therefore, the polysilicon gates 16 are shown shifted to the right, to simulate the result of a misalignment. When this type of misalignment occurs, the area in the diffusion regions 15 change, thereby causing a variation in output load capacitance. As shown, the first transistor device 14 is shown having a drain 15a that is substantially larger than the drain 15a' in the second transistor device 20. Similarly, the source 15b in the first transistor device 14 is substantially smaller than the source 15b' in the second transistor device 20.
Although these variations are known and anticipated by those who design semiconductor devices, when the circuits being fabricated are balanced circuits, these variations produce substantially inferior performance, especially when the balanced circuits are implemented in sense amplification devices that are used to detect very slight changes in voltage. Therefore, if the balanced circuit is implemented in a sense amplification device, the variations in capacitance produced by the misalignments of FIG. 1C will necessarily make it very difficult for the balanced circuit to detect very small changes in voltage, for example, a change in voltage from a pre-charge voltage level. In addition, because the drain 15a has a substantially larger capacitance (i.e., larger load) than drain 15a', the switching speed of the first transistor device 14 will be much slower than the switching speed of the second transistor device 20.
In sum, all of these local mismatches in balanced circuits generally force designers to accept circuit designs that are less than optimum. In fact, when the local mismatch becomes too large, the balanced circuit may even fail to operate for its intended purpose.
In view of the foregoing, there is a need for improved semiconductor device layout techniques that assist balanced circuits in being more resilient to fabrication imperfections that cause mismatches.